(a) Field of the Invention
The present invention relates to a tristate buffer having a bipolar transistor such as used in a BiCMOS semiconductor integrated circuit and, more particularly, to a tristate buffer used for a bus line connecting between different integrated circuits or between different circuit portions in a single integrated circuit.
(b) Description of the Related Art
Tristate buffer is generally used for a bus line connecting different integrated circuits or different circuit portions in a single integrated circuit. The tristate buffer functions for time sharing of bus line for data transmission without overlapping different signals. The tristate buffer assumes three logic states for signal transmission including high-level, low-level and high-impedance states.
When a high-level signal is to be held on the bus line, a tristate buffer which is in a state of outputting a low-level signal is maintained at a high-impedance state to avoid a signal overlap. The tristate buffer has input and output terminals for signal transmission and a control input terminal for effecting the high-impedance state or low-impedance state for outputting the high-or low-level signals. In current integrated circuits, CMOS transistors are widely used for a low power consumption and a high integration density instead of bipolar transistors, which have a high operational speed but have a lower integration density and consumes larger power. To take advantage of the high operational speed of the bipolar transistors, BiCMOS IC is also widely used wherein bipolar transistors and CMOS transistors are integrated in a single chip. The BiCMOS IC has advantages of low power consumption and high integration density compatible with a CMOS IC and an advantage of high operational speed compatible with the bipolar IC.
In general, the upper limit of the operational voltage of the transistors is reduced with the advance of the finer process for the transistors. Especially, bipolar transistors have a low reverse bias withstand voltage for the P-N junction between the emitter and base of the bipolar transistors. The overvoltage exceeding the reverse bias withstand voltage breaks-down the base-to-emitter P-N junction, with the result that a breakdown current flows from emitter to base, and the forward current gain of the bipolar transistor is markedly reduced to retard the high operational speed of the bipolar transistor.
In view of the above, some proposals have been given for a tristate buffer incorporating a bipolar transistor wherein an applied emitter-to-base reverse bias voltage does not exceed the withstand voltage of the same.
FIG. 1 shows a circuit diagram of one of tristate buffers implemented by a BiCMOS configuration and proposed in a Patent Publication No. JP-A-2(1990)-214219. In the tristate buffer, input terminal VIN is connected to an internal circuit and output terminal VOUT is connected to a bus line. It is assumed that the tristate buffer of FIG. 1 is in a high-impedance state while the bus line is maintained at a high level by the output signal supplied from another tristate buffer.
In this state, non-inverting logic control terminal VNE is applied with a high-level signal, and inverting logic control terminal VNEB is applied with a low-level signal, with the result that nMOS transistor 15, nMOS transistor 4 and pMOS transistor 13 are in OFF-state. As a result, output terminal VOUT and the base of NPN transistor 6 are in a high-impedance state wherein these nodes are separated from the source line or ground line. The base of NPN transistor 6 is coupled to the output terminal VOUT by nMOS transistor 14, to prevent a reverse bias overvoltage from being applied between the emitter and base for avoiding the breakdown of the P-N junction.
FIG. 2 shows another example of tristate buffers which is proposed in JP-A-4(1992)-43713. It is assumed that the inverting logic control terminal VNEB is applied with a high-level signal, with the result that the tristate buffer is in a high-impedance state. Specifically, the high level at the inverting logic control terminal VNEB turns nMOS transistor 2, nMOS transistor 7 and pMOS transistors 1 and 25 off, with the result that the output terminal VOUT and the base of NPN transistor 6 are clamped together to stay in a high-impedance state. In this case, the breakdown of the P-N junction is also avoided due to the equal potential of the base of NPN transistor 6 with output terminal VOUT. The two conventional tristate buffers have a substantially equal concept wherein a switching transistor is provided between the base and emitter of NPN transistor 6 to couple the base and emitter during a high-impedance state of the tristate buffer.
In both the tristate buffers as described above, if an overvoltage exceeding the supply voltage is applied to the output terminal, the overvoltage generates current flow through the output terminal VOUT into the source line VCC.
Specifically, the overvoltage in the first example of FIG. 1 raises the base voltage through nMOS transistor 14 above collector voltage by, for example, 2.5 volts, which generates base-to-collector forward current along the P-N junction formed between the base and collector. The overvoltage in the second example of FIG. 2 also raises the base voltage through pMOS transistor 16 above collector voltage, which also generates base-to-collector forward current along the P-N junction formed between the base and collector. In addition, pMOS transistor 1 which has been off before the entry of the overvoltage may be turned on by the overvoltage if the overvoltage is as high as, for example, 4 volts. In this case, the overvoltage also generates a current flow from output terminal VOUT through pMOS transistors 16 and 1 to the source line VCC.
The current caused by the overvoltage at output terminal VOUT raises the supply voltage VDD of the IC to thereby retard the normal operation of the entire circuit. In addition, the influence of the overvoltage depends on the number of tristate buffers incorporated in the circuit and the number of tristate buffers which are in a high-impedance state, with the result that the influence is difficult to evaluate beforehand in a LSI design.
The tristate buffer thus allowing the current flow by the overvoltage suffers from a large power consumption in the another tristate buffer, which maintains the bus line at a high level, as well as a temperature rise in the transistors in the tristate buffer shown in the figures.